Assigning queues in system verilog

In reply to confused kid:
I am trying to help you, but you are making it very difficult and not putting enough effort to show working code and expected output. Your C++ code produces no output because y is all 0 and you are iterating over
for(int i;y)
. Also, the code you just showed now has 4 nested loops, but your original code had only 2. Anyways, here is the your non-working code translated to SystemVerilog

module top;
   
   int h[8]= {0,1,2,3,4,5,6,7};
   int x[8] = {1,2,1,1,2,2,1,0};
   int y[8] = '{default:0};
   
initial
  foreach(y[ii]) begin : loop1
     int i;
     i = y[ii];
     while(--i > 0) begin : loop2
	for(int n = 0; n < 8; ++n) begin : loop3
	   automatic int sum = 0;
	   for(int k = 0; k < n; ++k)begin : loop4
	      sum += h[k]*x[n-k];
	   end : loop4
	   y[n]= sum;
	end : loop3
	foreach(y*) $display(y[i]);
     end : loop2
  end : loop1
   
endmodule : top

The foreach loop replaces C++ range-based for loop.
By default, all variable declarations outside of classes are static variables. If you want a loop variable initialized each time through the loop, you have to declare them as automatic, or split the declaration and initialization into separate lines.
I added optional block labels to make the code easier to follow (loop1,…)

[i]In reply to confused kid:*
You don’t have to put variables in a class to randomize them, you can call std::randomize(x). You have to put that in your procedural code, not as part of the variable declaration. randomize() returns true or false depending on the success of the randomization.

if ( !std::randomize(h)) with {foreach(h[k]) h[k] inside {[0:8]};} )
       $error("randomization failed");