Assigning module variables from an Interface

Hi All ,

Generally interface is passed as part of module port_list and within the module , variables declared within the interface are assigned in the module.

I tried the reverse in below code

interface  intf ;
   //  Assigns  the  module  level  variables . 
   function  automatic void  ASSIGN( input logic [4:0] ip_a , input logic [3:0] ip_b );

      csr.reg_a = ip_a ; 
      csr.reg_b = ip_b ;



module  csr ;

 logic [4:0] reg_a ;
 logic [3:0] reg_b ;

 intf  intf0 ();


module top ;

 csr  CSR(); 

 initial  begin

   CSR.intf0.ASSIGN( 10 , 4 );

   $display(" reg_a == %0d " , CSR.reg_a );
   $display(" reg_b == %0d " , CSR.reg_b );



I observe that the code works but I do not quite get the following ::
How is that there is No compilation / elaboration time error when accessing csr.reg_a / csr.reg_b within the interface ?

Does an interface have an implicit access to all the variables of the module within which it’s instantiated ?

In reply to Have_A_Doubt:

This is known as an hierarchical upward name reference. It works the same for modules and interface instances. See section 23.8 Upwards name referencing in the IEEE 1800-2017 SystemVerilog LRM

A full hierarchical reference to your top-level module is the same thing as an upward reference. (i.e. top.CSR.reg_a)

In reply to dave_59:

Thanks Dave .

Have 1 last question .

As the name suggests “hierarchical upward name reference”

This means that variables in 1 / 2 / N hierarchy upwards can be assigned using simply the module_name. ( provided there is a hierarchical relation between them. )

Hence CODE1 is legal whereas CODE2 isn’t legal .

Is my understanding correct ?

In reply to Have_A_Doubt:

Correct. The module_name has to be in the upwards hierarchical scope. If you had more than one instance of module csr, would be ambiguous which one you are selecting.