Assigning local variable within 'or' V/S 'and' operator

SystemVerilog
,
8

In reply to ben@SystemVerilog.us:

For the following sequence


sequence s1;
    int x;
 ( a ##1 b, x = data , $display("T:%0t For 1, x == %0d ",$time,x ) ) // seq1
    and 
 ( ( d ##1 e, x = data , $display("T:%0t For 2, x == %0d ",$time,x ) ) ##1 (data1 == (x + 1) )  );  //  seq2
  endsequence

Scope of local variable ‘x’ is within sequence s1.This means seq1,seq2 both have access to it.

It behaves as 2 separate variables, one for each sequence.

So seq1 isn’t aware whether seq2 assigns to it as well. Essentially behaving as 2 separate variables