Assigning local variable within 'or' V/S 'and' operator

SystemVerilog
,
7

In reply to Have_A_Doubt:
It behaves as 2 separate variables, one for each sequence. Thus, it is equivalent to:


sequence s1;
    int x1, x2;
 ( a ##1 b, x1 = data , $display("T:%0t For 1, x1 == %0d ",$time,x ) ) // seq1
    and 
 ( ( d ##1 e, x2 = data , $display("T:%0t For 2, x == %0d ",$time,x ) ) ##1 (data1 == (x2 + 1) )  );  //  seq2
 
  endsequence
  ap4:assert property( @(posedge clk) s1);