Assigning local variable within 'or' V/S 'and' operator

SystemVerilog
,
6

In reply to ben@SystemVerilog.us:

Ben,
So in the following case


sequence s1;
    int x;
 ( a ##1 b, x = data , $display("T:%0t For 1, x == %0d ",$time,x ) ) // seq1
    and 
 ( ( d ##1 e, x = data , $display("T:%0t For 2, x == %0d ",$time,x ) ) ##1 (data1 == (x + 1) )  );  //  seq2
       
  endsequence
  ap4:assert property( @(posedge clk) s1);

There is no error ( although local variable ‘x’ is assigned in both LHS (seq1) and RHS (seq2) sequence of ‘and’ operator ) as there is no discrepancy
for which value of ‘x’ is being used in expression: data1 == ( x + 1 ) i.e the value of ‘x’ assigned in seq2 is being used expression