In reply to ben@SystemVerilog.us:
Ben,
I was trying a few variations in the code.
I notice that following code is legal: edaplayground
whereas if I add a parenthesis around the ‘and’ operator, the sequence s1 is illegal ( for reasons pointed by you above )
sequence s1 ; // Gives compilation error
int x ;
(
( a ##1 b, x = data , $display(" For 1, x == %0d ",x ) )
and
( d ##1 e, x = data , $display(" For 2, x == %0d ",x ) )
) // Added parenthesis around the 'and' operator
##1 ( data1 == ( x + 1 ) ) ;
ensequence
I am trying to understand without the parenthesis around the ‘and’ operator, how is the sequence ‘s1’ interpreted ? i.e Why is it legal that way ?