Assigning different clock for a interface array

SystemVerilog
8

In reply to dave_59:

I tried this code without uvm, it works fine, the data signal change on each clock assigned to the interfaces, is it possible that uvm_config_db did something to the virtual interface so that the signals in drv and mon does not perform as I expected?
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interface type_rx_if(input bit clk);

wire  done; 	
   clocking mck @(posedge clk);
      inout  done;
   endclocking: mck
   
   modport master(clocking mck);
  
endinterface


module test ();
reg  reset, clk, clk_sfp ;

  type_rx_if rx_vif[3:0] ({clk_sfp,{3{clk}}});
  

    initial begin
    clk <= 1'b0;
	   clk_sfp <= 1'b0;
	   #200;
	   rx_vif[3].mck.done <= 1'b0;
	   rx_vif[0].mck.done <= 1'b0;
	   #200;
	   rx_vif[3].mck.done <= 1'b1;
	   rx_vif[0].mck.done <= 1'b1;	   
    end

  always
    #62.5 clk = ~clk;
  always
  	#40 clk_sfp = ~clk_sfp;


endmodule