clk1 and clk2 are not related,
I just worked the tb out with only clk1, now I want to change the clock domain of some interface and the corresponding drv, mon, I don’t want to modify the code of drv and mon. so I try to only modify the instantiation of the interface on the top level. is there some potential reasons that will cause bug with this. I just checked the waveform, the clock in the interface is correctly connected, but the signals in the drv and mon still change on the same clock.