Assigning a constant value to an unpacked array

SystemVerilog
,
1

Hello,
I need to assign a constant value ‘0’ to an unpacked array.
My array is defined as “reg [3:0] q [1:0]”.
Can this be done using the streaming operator?
What is the standard way of doing this?

Thank you.

2

This will assign 0 to every element in an array:

q = '{default:0};

By the way, you should stop using the reg keyword. Use logic or bit. See What's the deal with those wire’s and reg’s in Verilog - Verification Horizons

1 Like
3

To clarify, you want to make every element in your array the contant value ‘0’


module test();
        reg [3:0] q [1:0];

        initial begin
                $display("q is %p",q);
                q = '{2{'0}};
                $display("q is %p",q);
        end
endmodule
4

In reply to alexgran:

Thanks.
That did the trick.
And you’re right, I should use bit instead.
Old verilog habits die hard :)

5

In reply to alexgran:

Maybe it works only inside an initial block? I tried putting this code inside my clocking block and did not seem to work. But the q = '{default:0}; worked.