Assign associating with index and element in an array

SystemVerilog
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1

I want to assign values by system verilog .For example, given an array a = {4, 7, 5, 8, 3}, i want to assign Y = X, where X is an identifier related to the index value of array a, such as xi, and Y is an identifier related to the array elements, such as ya[i]. The specific assignments are as follows: y4 = x0, y7 = x1, y5 = x2, y8 = x3, y3 = x4.I know I can use an enumeration approach, but is there a faster method?

2

In reply to zygu:

This is an XY Problem.

You cannot build identifiers at run time from the values in other variables.

You need to explain why you cannot use an array of variables.
Otherwise, You could use case statements to select individual variables.

foreach (a[I])
 begin
   case (I)
    0: tmp = x0;
    1: tmp = x1;
    2: tmp = x2;
    ...
   endcase
   case (a[I])
    0: y0 = tmp;
    1: y1 = tmp;
    2: y2 = tmp;
    ...
   endcase
  end