In reply to shivamdec:
******* PLEASE SEE MY CORRECTIONS BELOW THIS POST ********
I see the issue here.
1800’2012 says that a sequence is
expression_or_dist throughout sequence_expr
// and it is NOT the following
sequence throughout sequence_expr // ILLEGAL !!!!
What we have is
##1 ($stable(gray_count) || gray_count === "X") // a sequence
throughout (iso_input[->1]) // thus it is illegal
My tool is in error.
************** NOTE *************
[Ben] Errata: My tool is not in error, see my last post below
The fix:
ap_gray_cnt_value_chk: assert property(
@(posedge clk ) (start_addr == 'h10 && iso_input) |->
##1
( // expression_or_dist throughout sequence_expr
($stable(gray_count) || gray_count === "X") throughout
(iso_input[->1])
)
);
// ANOTHER FIX
ap_gray_cnt_value_chk: assert property(
@(posedge clk ) (start_addr == 'h10 && iso_input) |=>
($stable(gray_count) || gray_count === "X") throughout
(iso_input[->1])
);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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