Assertions - Temporal LHS error in throughout operator

SystemVerilog
5

In reply to ben@SystemVerilog.us:

Thanks for explanation. But I am getting same error again :(

Error-[SVATHTLHS] Temporal LHS of ‘throughout’ operator.

A temporal LHS is not allowed with the ‘throughout’ operator.
Expression: (( ##1 ($stable(gray_count) || (gray_count === “X”))) throughout
(iso_input [-> 1]))

property p_gray_cnt_value_chk;
      @(posedge clk ) (start_addr == 'h11 && iso_input) |-> ##1 ($stable(gray_count) || gray_count === "X")  throughout (iso_input[->1]);
endproperty

Is it some tool issue?
Using this VCS_MX version: vcs-mx_vK-2015.09-SP2-13-T0428

Thanks for coping up.