Assertions system verilog - question on $changed concurrent assertion

SystemVerilog
5

In reply to ben@SystemVerilog.us:

Thank you so much Ben.

Following doesn’t seem to work. I might’ve made a small error, not able to understand. There are bunch of fails before it passes. I just want to know if this passes or fails for the entire simulation.

interface sample ;
 //------------------------------------------
 // Signal Instantiation 
 //------------------------------------------
 logic x;
 logic clk;
 logic rst_n;
 logic y;
 logic z;



property name_1(clk,x,y);
  @(negedge clk)   
  $rose(x) ##[10:50] y;
endproperty

Reset_test_dmgr :
  assert property(name_1(clk,x,y))
    $display("time:%t assertion passed -- first, pmsb_side_rst_b", $time);
  else
    $display("time: %t assertion failed -- first, pmsb_side_rst_b", $time);

property name_2(clk,z);
  @(negedge clk) 
  $rose(z);
endproperty

Reset_test_dmgr_punit : 
  assert property(name_2(clk,z))
    $display("time:%t assertion passed -- second", $time);
  else
    $display("time: %t assertion failed -- second", $time);

endinterface: