In reply to shashankadimulam:
One can be tricked by speed reading, as I failed to notice that you declare an immediate assertion instead of a concurrent assertion. Specifically, you had
assert name(clk,rst_n,sig_a,sig_b
$display("time:%t assertion passed ", $time); ..
//It should have been
assert property (name(clk,rst_n,sig_a,sig_b))
$display("time:%t assertion passed ", $time);
I am surpised that your compiler did not pick this up as an error.
Below is code with a quick testbench. TO minimize my mistakes, I use the following tools:
- https://www.phraseexpress.com It is an Autotext and Text Autocompletion in any application and allows me to include boilerplate templates for SystemVerilog including a quick testbench.
- A quick testbench for my assertions. The testbench shown below was generated with my template using PhaseExpress; you define what is in the template.
- Visual Studio Code https://code.visualstudio.com A not too bad SystemVerilog editor that understands SystemVerilog and SVA. It is free, includes the syntax, and a “reindent lines”.
Of course, this editor does not have all the bells and features of commercial editors, but ti is not too shabby!
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, rst_n;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
property p_ab (clk,rst_n,sig_a,sig_b);
@(posedge clk) disable iff (!rst_n)
$changed(sig_a) |-> ##[1:2] sig_b;
endproperty
ap_ab: assert property (p_ab(clk,rst_n, a, b) )
$display("time:%t assertion passed ", $time);
else
$display("time: %t assertion failed ", $time);
initial begin
bit va, vb, vc;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb, vc) with
{ va dist {1'b1:=1, 1'b0:=3};
vb dist {1'b1:=1, 1'b0:=4};
vc dist {1'b1:=10, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
rst_n <= vc;
end
$stop;
end
endmodule
// simulation
time: 1500 assertion passed
# time: 4100 assertion passed
# time: 4700 assertion failed
# time: 4900 assertion passed
# time: 5900 assertion passed
# time: 6500 assertion failed
# time: 9700 assertion failed
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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