In reply to ben@SystemVerilog.us:
I modified and it doesn’t seem to work. Change happens on the sig_a at some random time, but as soon as this change is detected, sig_b should go high in the from 10:30 clock cycles.
I’m not sure why nothing gets printed. If the assertion is not true, at least it should print the fail statement, right?
Can you please advise on what’s wrong as I’m literally confused.
Thank you so much