In reply to ben@SystemVerilog.us:
I forgot to explain that a master is driving the PADDR line and a slave is driving the PREADY line. When a transition occurs on the PADDR line, this triggers the slave to do some work and after a random number of PCLKs (bigger than 1) the slave gives a PREADY signal that lasts only one PCLK. So I need to check that the PADDR line is stable throughout the interval of time that beggins when a PADDR transition occurs until the PREADY signal becomes one, the whole time.
Here’s a URL to an image which demonstrates a cycle.
So if I understood you well, I have mistakenly written an assertion that just checks if PADDR is stable only when PREADY arrives (becomes 1) but not throughout the whole cycle?