Your assertion looks OK unless you want the stability when PREADY==1.
2 options
property stable_paddr;
@(posedge PCLK)
disable iff (!PRESETn)
$changed(PADDR) |=>
strong(first_match($stable(PADDR) [*1:$] ##1 $rose(PREADY)) ##0 $stable(PADDR));
endproperty
// you can also consider the use of the s_unti_with
property stable_paddr2; //
@(posedge PCLK)
disable iff (!PRESETn)
$changed(PADDR) |=>
$stable(PADDR) s_until_with PREADY ##0 $stable(PADDR);
endproperty
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
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