Assertions not triggering:

SystemVerilog
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In reply to Bhaskar44:

In reply to ben@SystemVerilog.us:
However, I can’t use clk in my assertions module as it is a system clock and I am just checking the functionality of a an individual module of the DUT…
The DUT runs on the system clock, and assertions are written in a separate module and is bound to the DUT using the “bind” construct.

I fail to understand why you can’t use the DUT clk in the bind. The bind is like instantiating a module (or a checker) inside the DUT; thus, the clock can be passed as an actual argument.

So, I would have to approach this issue differently and help is much appreciated.

See if you can get access to the clock with the bind.
If you still can’t, and you must use a signal as the clocking event, then in your verification module you need to generate a secondary clock based on that event. For example:

 
bit a, b, c, a_chk; 
// a, b, c, are clocked at posedge clk. 
// clk period > 5 (in this example) 
always  @(a)  begin 
  #5 a_chk <= a; 
end 
apa_b: assert property(
   @(negedge a) |-> @(negedge a_chk) b );  
// b is sampled delta time before negedge a_chk,
//  but b has now settled in value

The above is quirky. I strongly recommend that you gain access to the system clock with the bind.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us