Assertions not triggering:

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Thanks for a detailed response.

However, I can’t use clk in my assertions module as it is a system clock and I am just checking the functionality of a an individual module of the DUT…

The DUT runs on the system clock, and assertions are written in a separate module and is bound to the DUT using the “bind” construct.

So, I would have to approach this issue differently and help is much appreciated.

Thanks