Assertions for Two clock cycles

SystemVerilog
,
6

In reply to ben@SystemVerilog.us:
My co-author and colleague Srinivasan Venkataramanan suggested a simpler approach, here it is:
(2) - EDA Playground code
EPWave Waveform Viewer // wave


 property p_clk1_v2; 
    bit vclk1; 
    @(posedge sp_clk1) go |->  
    @(posedge clk10) ##1 (1, vclk1=clk1) ##1 clk1==vclk1[*4] ##1
     ( ($changed(clk1), vclk1=clk1) ##1 clk1==vclk1[*4]) [*3];
 endproperty
    
 ap_clk1_v2: assert property(p_clk1_v2) pass1=pass1+1; else fail1=fail1+1;