Assertions For Data Integrity

SystemVerilog
, , ,
1

I was wondering whether we can use assertions for Data Integrity
I came across this data integrity check for a FIFO using assertions

output_data_integrity : assert forall dvalue in {0:255} :
always ( (push && data_in == dvalue) →
eventually! (pop && data_out == dvalue));

My Scenario :
After a Write Command Data comes after 10 clocks. This is a burst of data which comes for 4 clocks
After a Read , Data comes after 8 clocks. This is a burst of data of 4 clocks.
The Write and Reads can be issued in any order to any address.

Can we write an assertion for this scenario.

2

In reply to Jack Bryan:

The “forall” isn’t in c a.
Write a scoreboard using the high-level structures of SV.
Use SVA to compare the results of the dut against the scoreboard.
Ben systemverilog.us