Assertions fails in frequency checking

SystemVerilog
,
1

Hi ,
Wrote assertion for frequency check, when the value are same displaying .Assertions are still failing for 0.2nsand 1.6ns .The assertions are getting passed in 50ns .

timescale 1ns/1ps
realtime period_5g=0.2ns;
realtime period_20m=50ns;
realtime period_625m=1.6ns;
realtime period;

property clk_freq_chk(logic data_rst_n,realtime period) ;
realtime current_time;
realtime next_time;
disable iff (data_rst_n == 0)
('1, current_time = $realtime) |=> (1, $display (“p=%t,derived value=%t”, ($realtime - current_time),period))
// ('1,current_time = $realtime ) |=> ($realtime - current_time== period);
endproperty

CLK5G_p_chk:assert property(@(posedge i_clk5G_p) clk_freq_chk(data_rst_n,period_5g))
else $error(“clk5G_p incorrect”);

p=0.200ns,derived value=0.200ns

p=1.600ns,derived value=1.600ns

p=0.200ns,derived value=0.200ns

even though are same values are calculated in assertion s they are getting failed.

regards
Darshan

2

In reply to darshankumarka_vlsi:


``` verilog

timescale 1ns/1ps
realtime period_5g=0.2ns;
realtime period_20m=50ns;
realtime period_625m=1.6ns;
realtime period;

property clk_freq_chk(logic data_rst_n,realtime period) ;
realtime current_time;
realtime next_time;
disable iff (data_rst_n == 0)
('1, current_time = $realtime) |=> (1, $display ("p=%t,derived value=%t", ($realtime - current_time),period))
// ('1,current_time = $realtime ) |=> ($realtime - current_time== period);
endproperty

CLK5G_p_chk:assert property(@(posedge i_clk5G_p) clk_freq_chk(data_rst_n,period_5g))
else $error("clk5G_p incorrect");




Adding the code tags to beautify the code.. it could be because that rst at the points of failure you mentioned could be x ?