Assertions Check if Signal is High when it enters a state and Stays High

In reply to dave_59:


// Is this what you need? 
//  A           0  0  1  1  1  1  1  X 
// FSM_WAIT     0  0  0  1  1  1  1  0
 $rose(fsm_state==FSM_WAIT)  |-> $past(A) and 
           A until_with (fsm_state!=FSM_WAIT );

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

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