Assertion

In reply to ben@SystemVerilog.us:

In reply to bhajanpreetsinght:

  1. What are your requirements. Be clear about them. Try to make them in bullet points.
  2. Show code, and results. What are the issues.
    I don’t mind answering questions, but I am not going to guess as to what you are really asking or what issues you see.

It is a very tough question in this one please answer