In reply to ben@SystemVerilog.us:
In reply to bhajanpreetsinght:
- What are your requirements. Be clear about them. Try to make them in bullet points.
- Show code, and results. What are the issues.
I don’t mind answering questions, but I am not going to guess as to what you are really asking or what issues you see.
so to conclude I need to write a code something
If a&& b&&c&&d&&e capture time1;
If clockgated is low for two consecutive clocks capture time2;
Third requirements: difference between time1:time 2 should be equal to clockgate_hysteresis value,if this happens pass if not fail