In reply to christin kripa John:
The easiest solution is explained in my paper
Dynamic delays and repeats
ISSUE: Using dynamic values for delays or repeats is illegal in SVA; how can this be easily resolved?
int dly1=2, dly2=7; // module variables
ap_abc_delay: assert property($rose(a) ##dly1 b |-> ##dly2 c); // ILLEGAL SVA
ap_abc_repeat: assert property($rose(a) |-> b[*dly1] ##1 c); // ILLEGAL SVA
SOLUTION: The concept is very simple, the repeat or delay sequence is saved in a package with two defined sequence declarations that include arguments.
http://SystemVerilog.us/vf/sva_delay_repeat_pkg.sv
package sva_delay_repeat_pkg;
sequence dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
sequence dynamic_delay(count);
int v;
(1, v=count) ##0 first_match((1, v=v-1'b1) [*0:$] ##1 v<=0);
endsequence
endpackage
// The package can be applied as follows:
// SystemVerilog.us/vf/sva_delay_repeat.sv
import sva_delay_repeat_pkg::*;
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, c=1;
int r=2;
default clocking @(posedge clk); endclocking
sequence q1; a ##1 b; endsequence
ap_abr: assert property(a |-> dynamic_repeat(q1, r) ##1 c);
ap_delay:assert property(a |-> dynamic_delay(r) ##0 b);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
FREE BOOK: Component Design by Example
… A Step-by-Step Process Using VHDL with UART as Vehicle
http://systemverilog.us/cmpts_free.pdf