Assertion - which assertion should I use and where?

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Each rd_en must followed by xn_valid.

//                0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
// rd_en          0  0  1  0  1  1  0  0  0  0  1  0  0  0  0  0
// xn_valid       0  0  0  0  0  0  0  1  0  1  1  0  0  0  0  1    
//                      ^--------------^
//                            ^--------------^
//                                ^-------------^
//                                              ^--------------^