In reply to ben@SystemVerilog.us:
In reply to bhajanpreetsinght:
@(posedge clk) $rose(c) |-> ((a||c) throughout(c==1)) until (c==0)
which also can be rewritten as
@(posedge clk) $rose(c) |-> ((a||c) && (c==1)) until (c==0)
it can be further rewritten as
@(posedge clk) rose(c) |-> ((a||c) && (c==1))[*0:] ##1 (c==0)
I suggest that you try various tests with different assertions; this will help in your
understanding of these operators. Also, read my paper Reflections on Users’ Experiences with SVA, part 2
Reflections on Users’ Experiences with SVA, Part II
Addresses the usage of these four relationship operators: throughout, until, intersect, implies
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
http://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog
https://rb.gy/f3zhh
Hi Ben,
I am asking a very dificult question
i know the concept of your dynamic delay which states like below
(count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);// in my case consider the count variable to be clkgate_hysteresis which is [11:0] variable .
now my antecedent is dependent on 5 variable which is
a && b && c && d && e throughout count|-> (count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0)##0 final variable =0;
so this assertion I am checking value a b c d e should be high throughout count which here count represent clock edges number which will be given dynamic and same clockedge numbers will be used as consequent to check the final variable is 0 after that many clock edge numbers.
Suppose clockedge number ='h10 so decimal 16, so assertion means till 16 clockedge a b c d e should be high and after that we would check the consequent which will trigger at same clock edge number 16 to check final variable is 0 and should reamin 0 atleast for 3 clock edge.
Request you to help with the code I have written pseudo cod eto please help me complete this assertion