Assertion to check that data does not toggle more than once when valid is low

SystemVerilog
,
1

I want use assertion to check that data does not toggle more than once when valid is low.
Assertion I tried:

 property no_data_toggle_when_no_vld;    
          @(posedge clk) disable iff(!reset)
          if(!vld)
          ($fell(vld) |-> !($changed(data))[*1:$] $stable(data));
        endproperty
        data_toggle_check: assert property(no_data_toggle_when_no_vld)
        else $display("ASSERT_ERROR: Assertion Failed :no_data_toggle_when_no_vld ");

Check what I Intend to is what I have put there. However I see syntax issue as I should use $stable with out mentioning time.
Can anyone please help here.