In reply to ben@SystemVerilog.us:
Thanks Ben,
// To avoid multiple threads, you could do the following:
initial begin
wait(rst==1’b0); // use whatever variation you need)
assert_check: assert property(@(posedge clk) disable iff(rst)
$rose (signal)[->1] |=> always(
!$isunknown(signal) && $stable(signal)); // else $error();
end
I tried your suggestion like below; as i want to check this for few sets of signals; when i compile hit with syntax error: "token is ‘always’. (using synopsys)
property xx_chk (logic a, logic b);
@(posedge clk) disable iff(rst)
$rose(a)[->1] |=> always (!$isunknown(q) && $stable(q));
endproperty
xx_check: assert property (xx_chk(dut.signal1, dut.signal2)) else $error();
tried
$rose(a)[->1] |=> ##30 (!$isunknown(q) && $stable(q)); // this works, but it checks once and not till simulation end.
me requirement is to check HIGH for all remaining clk cycles.