Assertion to check stability of a signal for 'n' clocks

SystemVerilog
,
6

In reply to Jayaraj:

In reply to ben@SystemVerilog.us:

one addition to above; the signal which i check want to be HIGH for all remaining clk cycles & it should not go unknown(X).
assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |=> !($isunknown (signal)) & stable(signal)[*]) else $error();[/quote]
Change the above assertion to:


// [*$] is illegal, use the always(property) 
// 1800 
// property_expr ::= .... 
//     always property_expr
//  | always [ cycle_delay_const_range_expression ] property_expr
//  | s_always [ constant_range] property_expr
//   Do you need the $error?  Ok if you want it. 
assert_check: assert property(@(posedge clk) disable iff(rst) 
   $rose (signal) |=> always( 
               !$isunknown(signal) && $stable(signal)); //  else $error();

// To avoid multiple threads, you could do the following: 
initial begin 
  wait(rst==1'b0); // use whatever variation you need) 
  assert_check: assert property(@(posedge clk) disable iff(rst) 
   $rose (signal)[->1] |=> always( 
               !$isunknown(signal) && $stable(signal)); //  else $error();
end

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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