Assertion to check stability of a signal for 'n' clocks

SystemVerilog
,
5

In reply to ben@SystemVerilog.us:

Hi Ben,

i want to check an assertion similar;
LEGAL: assert property(@(posedge clk) disable iff (rst) $rose (signal) |=>
$stable(signal)[*5]);

one addition to above; the signal which i check want to be HIGH for all remaining clk cycles & it should not go unknown(X).

assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |=> !($isunknown (signal)) & stable(signal)[*]) else $error();

pls advise.
Thanks