Hi, I want to check the stability of a signal for five clocks after it goes high. Like, once the signal goes high then it should remain ‘1’ for next five clocks. I have written the assertion in the below way. assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |-> signa…

In reply to sanjay864u : assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |-> signal[*5]) Can we make it more efficient? That is the correct and only way; a procedural concurrent assertion (e.f. always @(posedge clk) ) is not more efficient. However, you mention th…

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Assertion to check stability of a signal for 'n' clocks

SystemVerilog

sanjay864u April 11, 2016, 4:32pm 3

In reply to ben@SystemVerilog.us:

Thank you Ben…