In reply to sanjay864u:
assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |-> signal[*5])
Can we make it more efficient?
That is the correct and only way; a procedural concurrent assertion (e.f. always @(posedge clk) ) is not more efficient. However, you mention that signal should remain ‘1’ for next five clocks, meaning for 5 more clock cycles. You would need the |=> instead of the |-> since *$rose[a) |-> a[1] is valid for the cycle in which $rose(a) occurred.
assert_check: assert property(@(posedge clk) disable iff (rst) $rose (signal) |=> signal[*5])
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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