In reply to ben@SystemVerilog.us:
**Warning-[LCA_FEATURES_ENABLED] Usage warning
LCA features enabled by ‘-lca’ argument on the command line. For more
information regarding list of LCA features please refer to Chapter “LCA
features” in the VCS Release Notes
Parsing design file ‘design.sv’
Parsing design file ‘testbench.sv’
Top Level Modules:
duty_cycle
TimeScale is 1 ns / 1 ns
Error-[SVA-SCSE] Single-clocked sequence expected
testbench.sv, 17
duty_cycle, "ap_positive_duty_cycle_ch: assert property(positive_duty_cycle_chk(clk, 0.10000000000000001, 0.10000000000000001, 1)); "
Single-clocked sequence expected in operand of ‘repetition’ operator,
multi-clocked sequence found.
1 warning
1 error
CPU time: .134 seconds to compile
Exit code expected: 0, received: 1**
I just ran your code on EDA playground and got this error.