In reply to ben@SystemVerilog.us:
Hi Ben,
I’m implementing clock DCC checker using SVA. I want to only check the duty cycle in the first 2 clock cycles after id goes to 4’h2. When I use the repetition operator, compiler is throwing an error saying ‘repetition operator not allowed in multi-clocking sequence’
property positive_duty_cycle_chk(clk, real tolerance, real half_duty_cycle, id);
real v_t1, v_t2, v_hi, v_lo, v_diff, v_total;
real ratio;
@(id) id== 4'h2 |=> (@(posedge clk) (1, v_t1=$time) ##0 @(negedge clk) (1, v_t2=$time, v_hi=v_t2-v_t1) ##0 @(posedge clk) (1, v_lo=$time-v_t2) ##0
(1, v_total = (v_lo+v_hi)) ##0 (1, ratio = (v_lo* (1/v_total))) ##0 ratio >= half_duty_cycle - tolerance && ratio <= half_duty_cycle + tolerance) [*2];
endproperty
Can you please tell me how to fix this?