In reply to yourcheers:
In reply to ben@SystemVerilog.us:
Hi Ben,
What is the use of ##1, in the above property? Isn’t that just moving the assertion success just clock ahead?
$stable(b) requires information about the previous sampling cycle. In the very first cycle, the previous sample value is its default or initial value.
This can yield an unexpected error.
Isn’t that just moving the assertion success just clock ahead?
No; $fell(a) is sampled in cycle 2, 3, 4,
NOTE:$fell(a) is not sampled in cycle 1.
Without that ##1, $fell(a) is sampled in cycle 1, 2, 3, 4,…