In reply to ben@SystemVerilog.us:
Try this code.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk0, clk, a, c, refclk, sysclk, window;
bit va, vb, vc;
realtime period =20ns;
event ec, e1, e2;
realtime ta1, tc, done, active;
int count;
default clocking @(posedge clk);
endclocking
initial begin
repeat(90) @(posedge refclk);
forever @(posedge refclk) sysclk=!sysclk;
end
initial begin
window=1'b1;
repeat(120) @(posedge refclk);
window=1'b0;
end
initial forever #(period/2) clk0=!clk0;
initial forever #(period/2) refclk=!refclk;
always @(clk0) begin
#1 clk <= clk0;
if(vb) #3 c <= clk0;
else c <= clk0;
end
property p_c;
realtime t;
@ (posedge clk) (a, t=$realtime) |-> @ (posedge c) ($realtime==t);
endproperty
ap_c: assert property(p_c);
//
ap_ac: assert property(@ (posedge clk) $rose(a) |-> (1, t_check()) );
/*I need to check whether the clock sys_clk toggles within 80 clock cycles of en going low.
I have a reference clock named refclk to time the assertion.
The assertion should fail if the clock sys_clk does not toggle within the specified time.
I tried your solution but it does not fail when sys_clk is not toggling.
Because the fork waits for posedge of the clock and never fails.*/
initial t_check();
task automatic t_check();
automatic realtime ta1, tc, done, active;
int count;
$display("%t start of task ", $realtime);
while (window) begin : while1
fork
begin : chk1
//@ (refclk);
count = count+1'b1;
if(count>= 80) done=1'b1;
-> e1;
end : chk1
begin : chk2
@(posedge sysclk);
active=1'b1;
-> e2;
end : chk2
join_none
a_intask: assert(!done || active) else $display ("%t sysclk is not active ", $realtime);
$display("%t ta1= %t tc=%t", $realtime, ta1, tc);
if(active) -> ec;
active=1'b0;
@ (refclk);
end : while1
endtask
// here you can use # delays, wait statements, @ (posedge clk),
// fork other tasks, or whatever you need to verify your requirements
/*initial begin
repeat(200) begin
@(posedge clk0);
if (!randomize(va, vb, vc) with
{ va dist {1'b1:=10, 1'b0:=1};
vb dist {1'b1:=1, 1'b0:=2};
vc dist {1'b1:=1, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error")
#3;
a <= va;
end
$stop;
end */
endmodule