Assertion to check signal change only once(1->0->1) between 2 events

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

In reply to mlsxdx:


property b_chg_once_ac_within(s, e, b);
@(posedge clk)
$rose(s) |-> (##1 $fell(b)[->1] ##1 b[=1]) within e[->1];
endproperty

I tried the solution, it is still not fail when b changed twice.