Assertion to check signal activity occurred in past from current activity

SystemVerilog
, ,
4

I tried the below approach but it didn’t help. (I think assertion is neither passed nor failed)

property cnt_check(X);
int count;
@(posedge clk) (fell(A), count=X) ##1 ((!A && count==0), count=count-1)[*1:] |-> $fell(B);
endproperty

A2B_count_chk:assert property(cnt_check(X) $display(“PASSED at %t”, $realtime);
else $display(“Assertion failed at %t”, $realtime);

Please help me to find the problem in the above code.

Thanks,
Dhaval