Assertion to check req holds until ack

SystemVerilog
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6

In reply to ben@SystemVerilog.us:

If you want anassertion to meet your waveform where dcr_usr_rfsh_req==0 when
$rose(dsr_usr_rfsh_ack)==1 then do the following:

$rose (dcr_usr_rfsh_req) |-> 
  (dcr_usr_rfsh_req[*1:$] ##1 !dcr_usr_rfsh_req  intersect
  ($rose(dsr_usr_rfsh_ack)[->1] ##0 $fell(dcr_usr_rfsh_req)));

Hi Ben, I’ve tried the assertion code you’d suggested me above but my assertion still fail

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