Assertion to check req holds until ack

SystemVerilog
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In reply to lisa.lalice:
Your assertion does not meet the waveform you display
(dcr_usr_rfsh_req throughout ($rose(dsr_usr_rfsh_ack)[->1] ##0 $fell(dcr_usr_rfsh_req)));

1860×773 119 KB

1860×773 119 KB

If you want anassertion to meet your waveform where dcr_usr_rfsh_req==0 when
$rose(dsr_usr_rfsh_ack)==1 then do the following:

$rose (dcr_usr_rfsh_req) |-> 
  (dcr_usr_rfsh_req[*1:$] ##1 !dcr_usr_rfsh_req  intersect
  ($rose(dsr_usr_rfsh_ack)[->1] ##0 $fell(dcr_usr_rfsh_req)));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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