Assertion to check only one occurence of a pattern

SystemVerilog
, ,
2

In reply to Nagarjuna Chary:

Try the following, it is untested, but looks OK to me.


     property p_check_header; 
       bit [3:0] pattern_reg; 
       bit [1:0] num_header;
           @(posedge clk) ($rose(start), pattern_reg=0, num_header=0) |-> 
                         ( (1, pattern_reg = {pattern_reg,a}) ##0  
                           (1, num_header += pattern_reg==4'hF) ) [*30]  ##0 (num_header<=1);
     endproperty  
     ap_check_header: assert property( p_check_header) $display("Assertion Max PASS at time %t", $time); 
                                                   else $display("Assert MAX FAIL at time %t", $time);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: