Assertion to check number of ones is even!

SystemVerilog
, , ,
2

In reply to preetam_kale:

Refer to section 16.9.3 of the LRM which describes how to access the values used during the assertion.


module test();  
  bit clk;
  bit [15:0] a;
 
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
 
  property p1;
   @(posedge clk) (($countones(a)%2)==0);
  endproperty
 
  assert property(p1)
    $display("PASS\t[%0t] a:%b\tones:%d",$time, $sampled(a), $countones($sampled(a)));
  else 
    $display("FAIL\t[%0t] a:%b\tones:%d",$time, $sampled(a), $countones($sampled(a)));
 
  always @(posedge clk) begin	
    a <= $random;
  end
 
  initial begin
    #1000;
    $finish;
  end
 
endmodule