In reply to pvpatel:
In reply to ben@SystemVerilog.us:
What about if I want to see that signal sig2 should change only once during simulation after sig1 asserted and error should fire if changed more than once.
@(posedge clk) strong(##[1:$] $rose(sig1)) );
This assertion only check once and it will be finished.
Your above sequence (used as a property) does not meet your requirements as it makes no mention of sig2. Also, with what you wrote, if sig1 occurs after 1 million cycles, your assertion creates 1 million separate threads. The simulator may do some optimization.
Thus, for a single firing, put the assertion in an initial block.
assertions typically have an antecedent and a consequence. Something like:
ap_s1s2: assert property (@(posedge clk) $rose(sig1) |-> s_eventually sig2 );
ap_s1s2b: assert property (@(posedge clk) $rose(sig1) |-> strong(##[*0:$] sig2));
ap_s1s2c: assert property (@(posedge clk) $rose(sig1) |-> strong(sig2[->1]));
FOr and error should fire if changed more than once, consider the use of the cover
bit my_error; // If true, fire a message
cp_s1s2b: cover property (@(posedge clk) $rose(sig1) |-> (sig2[->2]) my_error <= 1'b1;
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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