Assertion to check for the toggle (0->1) of a signal

SystemVerilog
,
2

In reply to sanjay864u:
You need the strong ( sequence_expr ). I would then code this simply as:


assert_check: assert property (@(posedge clk) s_eventually $rose(sig1));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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