Assertion to check for the pulses of the clock

SystemVerilog
9

In reply to Lina.Lin:
10.34 Measuring clock periods // From my SVA book
User’s requirement: Check that the duty cycle of a clock is within acceptable limits.
The concept is simple: based on clock edges, measure the widths in which the clock is high and low, and compare the difference against an acceptable tolerance. The use of realtime type provides more accuracy. When using a concurrent assertion, local variables are used to hold the measured values. A multiclocking approach is used to trigger on each edge of the clock.

module timem; // /ch10/10.34/timem.sv
	timeunit 100ps; timeprecision 100ps;
	initial $realtimeformat(-9, 5, " ns", 10); // for display of time
	bit clk, a, b;
	property period_chk;
		realtime current_time, deltat; // deltat used for debug, as a temp
		('1,current_time = $realtime ) ##1
			(1, deltat=current_time) ##0 deltat == 10ns;
	endproperty
	ap_time: assert property(@(posedge clk) period_chk);
	property period_chk2;
		realtime current_time, deltat;
		('1,current_time = $realtime ) ##1
			(1, deltat=current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
	endproperty
	ap_time2: assert property(@(posedge clk) period_chk2); 
	
	// On multi-clocking, you can use something like
	property @(posedge clk) disable iff (reset); // 50mhz
		realtime t; 
		(scan_en == 1'b0, t=$realtime) |-> 
			@(negedge clk2)  (1, $realtime-t== 250ns, t=$realtime) ##0
			@(posedge clk2)  (1, $realtime-t== 250ns, t=$realtime);
	endproperty

Ben Cohen
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