Assertion to check for the pulses of the clock

SystemVerilog
8

In reply to durga:

If you only want to check the func_clk period, you need to capture its period first. see if the following code works for you.


  real prev_time, cur_time, periodT;
  parameter FUNC_CLK_PERIOD = 8;
  parameter SAMPLE_CLK_PERIOD = 2; //sample clk can be TB clk or internal design clock like non-gated version fun_clk.
  
  //capture func_clk period: periodT
  always @(posedge func_clk_used_in_capture_phase ) begin
    cur_time=$time;
    periodT=cur_time - prev_time;
    $display("prev_time =%0t, current_time=%0t, periodT=%0t",prev_time, $time, periodT);
    prev_time = $time;
  end

  property P_CHECK_FUNC_CLK_PERIOD_IN_CAPTURE_PHASE;
    @(posedge sample_clk) disable iff (reset || scan_en)
    $fell(scan_en) |-> ##[FUNC_CLK_PERIOD/SAMPLE_CLK_PERIOD-1:FUNC_CLK_PERIOD/SAMPLE_CLK_PERIOD+1] periodT==FUNC_CLK_PERIOD;
  endproperty
  
  assert property (P_CHECK_FUNC_CLK_PERIOD_IN_CAPTURE_PHASE) $display("Check periodT Success: periodT=%0t",periodT); else $error("Check periodT failed: periodT=%0t", periodT);