In reply to Lina.Lin:
In reply to ben@SystemVerilog.us:
You description regarding to the requirement is much clear, especially clarify sc_clk is a gated version of clk by scan_en.
The assertion is also implemented well, I read it and think maybe update is needed as below:
- change clock event from @(posedge clk) to @(negedge clk). Assertion evaluation uses sampled values (pre-clock values), so negedge clk will get sc_clk sampled to be 1 and posedge clk will sample sc_clk to be low.
My mistake on this. You’re correct. My fram of mind was more on the control to the clock gating than an assertion on the clock waveform; that is the first time I see such requirements. But I would write the assertion this way if I really wanted to check the clock waveforms:
ap_scan: assert property(@(posedge clk) disable iff (reset); // 50mhz
$fell(scan_en) |-> (@(negedge clk) sc_clk ##0 @(posedge clk) !sc_clk) [*N] ##0 @(negedge clk) !sc_clk[*2]);
// Typically, one deals with the control signsls. Thus, the forllowing would be correct
ap_scan: assert property(@(posedge clk) disable iff (reset); // 50mhz
$fell(scan_en) |=> sc_clk_enable[*N] ##1 !sc_clk_enable);
- add scan_en to the disable condition to disable check in case scan_en asserts to bring up sc_clk running again.
Wouldn’t that cause the miss of $fell(scan_en)
Ben SystemVerilog.us