In reply to ben@SystemVerilog.us:
line:1 let N=2;
line:2 ap_scan: assert property(@(posedge clk) disable iff (reset); // 50mhz
line:3 $fell(scan_en) |=> sc_clk[*N] ##1 !sc_clk);
// signal sc_clk ==1 @(posedge clk) N cycles following the $fell(scan_en)
// Following those N cycles, signal sc_clk ==0
Hi ben,
In line : 3
It is mentioned as sc_clk[*2]
My question is : Is the signal “sc_clk” is high for 2 consecutive “clk” cycles ???
Thanks
durga